A variety of integrated circuit devices, such as asynchronous dynamic random access memories (DRAMs), detect transitions of electrical signals from low to high or high to low logic states. For example, detecting transitions of selected signals is often used to produce a pulse to control equilibration in a memory array. To improve the performance of such devices, it is often desirable to detect such transitions as quickly and accurately as possible.
One approach to signal transition detection is shown in FIG. 1 where a transition detection circuit 38 detects transitions of an input signal S.sub.IN1 and outputs a detect signal S.sub.PT in response. In one application, the input signal S.sub.IN1 is a signal representing one bit of an address. The input signal S.sub.IN1 directly drives two inputs of a latch circuit 40 and is also inverted by an inverter 42 to produce an inverted input signal S.sub.IN1 * which drives two additional inputs of the latch circuit 40. Each of the noninverted and inverted input signals S.sub.IN1, S.sub.IN1 * is also delayed by a respective delay block 44, 46 to produce complementary delayed input signals S.sub.D, S.sub.D *. Each of the delayed input signals S.sub.D, S.sub.D* drives another two inputs of the latch circuit 40.
The latch circuit 40 includes two legs 48, 50 each formed from a series combination of two PMOS transistors 52, 54, 56, 58 and two NMOS transistors 60, 62, 64, 66 serially coupled between a supply voltage V.sub.CC and ground. A common pair of nodes 68, 70 between the lower PMOS transistor 54, 58 in each PMOS pair and the upper NMOS transistor 60, 64 in each NMOS pair forms the output of the latch circuit 40. One skilled in the art will recognize that the two nodes 68, 70 are electrically equivalent because they are electrically connected nodes. However, the nodes 68, 70 are treated separately herein to allow separate discussion of operation of the legs 48, 50.
Operation of the latch circuit 40 will now be described with reference to FIG. 2. As shown in FIG. 2, the input signal S.sub.IN1 is initially high, turning OFF the upper transistor 52 in the left leg 48 and turning ON the lower NMOS transistor 62 in the left leg 48. The inverted input signal S.sub.IN1 * is low, turning ON the lower PMOS transistor 58 in the right leg 50 and turning OFF the upper NMOS transistor 64 in the right leg 50.
The delayed input signal S.sub.D is also high initially, turning OFF the lower PMOS transistor 54 in the left leg 48 and turning ON the lower NMOS transistor 66 in the right leg 50. The delayed inverted input signal S.sub.D * is low, turning ON the upper PMOS transistor 56 in the right leg 50 and turning OFF the upper NMOS transistor 52 in the left leg 48.
Under these conditions, the OFF PMOS transistors 52, 54 and the OFF upper NMOS transistor 60 in the left leg 48 isolate the node 68 from the supply voltage V.sub.CC and ground, respectively. The OFF NMOS transistor 64 isolates the node 70 from ground. The ON PMOS transistors 56, 58 couple the node 70 to the supply voltage V.sub.CC so that the latch circuit 40 produces a latch output signal S.sub.P1 that is high.
At time t.sub.1 the input signal S.sub.IN1 transitions low. The inverted input signal S.sub.IN1 * transitions high very shortly thereafter, at time t.sub.2, due to the slight time delay of the inverter 42. The low input signal S.sub.IN1 turns ON the upper PMOS transistor 52 in the left leg 48 and turns OFF the lower NMOS transistor 62 in the left leg 48. However, the latch output signal S.sub.P1 remains high between t.sub.1 and t.sub.2 because the signals S.sub.IN * and S.sub.D * remain low to maintain the PMOS transistors 56, 58 ON. The inverted input signal S.sub.IN1 * transitions high at t.sub.2 to turn OFF the lower PMOS transistor 58 in the right leg 50 and turns ON the upper NMOS transistor 64 in the right leg 50. However, the delayed input signal S.sub.D remains high until t.sub.5 to maintain the PMOS transistor 54 in the left leg OFF and the NMOS transistor 66 in the right leg 50 ON. Thus, the ON NMOS transistors 64, 66 ground the node 68 at t.sub.3 while the OFF transistors 54, 58 isolate the nodes 68, 70 from the supply voltage Vcc, causing the latch output signal S.sub.P1 to transition low at time t.sub.3. The transition at time t.sub.3 follows the time t.sub.2 because the transition is delayed by the switching times of the transistors 54, 58, 64.
The low latch output signal S.sub.P1 pulls down one of the inputs to the NAND gate 72 which has its remaining inputs S.sub.P2 -S.sub.PN driven by additional transition detection circuits 38. If the remaining inputs of the NAND gate 72 are high, the NAND gate output will transition briefly from low to high. The output of the NAND gate 72 passes through the inverter 74 so that the detect signal S.sub.PT goes from high to low at time t.sub.4. The time t.sub.4 follows the latch output signal S.sub.P1 transition at time t.sub.3, due to the delays of the NAND gate 72 and the inverter 74.
While the above-described transitions are occurring, the transitions of input signal S.sub.IN1 and the inverted input signal S.sub.IN1 * are propagating through the respective delay blocks 44, 46 to produce transitions of the delayed signals S.sub.D, S.sub.D *. The transitions of the delayed signals S.sub.D, S.sub.D * reach the outputs of respective delay blocks 44, 46 at times t.sub.5, t.sub.6, respectively, as shown in the third and fourth graphs of FIG. 2. The transitioning delayed signal S.sub.D turns ON the lower PMOS transistor 54 in the left leg 48 and turns OFF the lower NMOS transistor 66 in the right leg 50. The OFF NMOS transistor 60 isolates the node 68 from ground while the ON PMOS transistors 52, 54 couple the node 68 to the supply voltage V.sub.CC. In response, the latch output signal S.sub.P1 returns high at time t.sub.7, which is slightly delayed with respect to the times t.sub.5, t.sub.6, due to the switching times of the transistors 54, 56. In response to the latch output signal S.sub.P1 going high, the detect signal S.sub.PT returns high at time t.sub.8 following the delays of the NAND gate 72 and the inverter 74. The output of the detection circuit 38 is thus a low-going pulse in response to a high-to-low transition of the input signal S.sub.IN1.
In a similar fashion, when the input signal S.sub.IN1 returns high at time t.sub.9, the inverted input signal S.sub.IN1 * returns low at t.sub.10. The high input signal S.sub.IN1 turns OFF the PMOS transistor 52 in the left leg 48 and turns ON the NMOS transistor 62 in the left leg 48. The delayed inverted input signal S.sub.D * remains high to keep the NMOS transistor 60 ON so that the node 68 is coupled to ground through the NMOS transistors 60, 62.
The delayed input signals S.sub.D and S.sub.D * transition high and low, respectively, at t.sub.13 and t.sub.14, respectively. The low S.sub.D * signal turns OFF the NMOS transistor 60 in the left leg 48 to isolate the node 68 from ground, and turns ON the PMOS transistor 56 in the right leg 50 to once again couple the node 70 to V.sub.CC. Thus, the PMOS transistors 56, 58 in the right leg initially couple the nodes 68, 70 to V.sub.CC. Responsive to the low transition of the input signal S.sub.IN1, the NMOS transistors 64, 66 transition the nodes 68, 70 low for a short period until the PMOS transistors 52, 54 in the left leg 48 couple the nodes 68, 70 to V.sub.CC. When the input signal S.sub.IN1 transitions back to high at time t.sub.9, the NMOS transistors 60, 62 in the left leg 48 couple the nodes 68, 70 to ground for a short period until the PMOS transistors 56, 58 in the right leg 50 once again couple the nodes 68, 70 to V.sub.CC.
As can be seen from the above discussion, the detect signal S.sub.PT responds to transitions at times t.sub.1, t.sub.9 with pulses that begin at times t.sub.4, t.sub.12, respectively. The output pulses are thus delayed with respect to the transitions by the intervals between time t.sub.1 and time t.sub.4 and between time t.sub.9 and time t.sub.12. The overall delay which results from the delays of the latch 40, the NAND gate 72 and the inverter 74 may be undesirably long for some applications. A more rapid detection of signal transitions would allow faster operation of memory devices.